The present invention generally relates to power consumption in memory circuits. More particularly, this invention presents a circuit and a method for memory sense amplifiers, which automatically limits the total power consumed by a sense amplifier.
A typical memory integrated circuit device such as a flash memory, contains several functional blocks which make up the whole memory system. For example, there is an address decode which takes the memory address bus as input and output word lines which select groups of memory cells for writing and reading. In addition, there are input data drivers which interface with the memory array data bit lines for purposes of writing new data into the memory cells. Then, there are the memory arrays themselves which are made up of memory cells. Sense amplifiers facilitate readings of data stored in the memory cells. The sense amplifiers sense the data level of bit-lines in order to sense (or read) the value of memory cells. The sense amplifiers interface with bit-lines, which are attached to the memory cells and with data output drivers (sense outputs), which are the output lines of the memory system.
During read operations, sense amplifiers are one of the circuit blocks that consume the most power. Pre-charging the bit-lines after reading also consumes a large amount of power, and the pre-charging circuits are often designed in conjunction with the sense amplifiers. Pre-charging is a way to restore bit-lines to an optimal operating region of the sense amplifiers, so that the memory cells can be read faster.
With greater memory density and increased commercial need, the power dissipation and speed of sense amplifiers are an important design criteria. Also, since any improvement to power consumed by sense amplifiers is magnified by the amount of memory, improvements to a sense amplifier design have a large impact in overall device performance. As such, there is a need for improved power performance in sense amplifier designs.